1. Field of the Invention
The present invention relates to a method of driving a plasma display panel and to a plasma display device. Particularly, the present invention relates to a driving method for reducing address current flowing in scan electrodes and for reducing the load on scan drivers or the number of the scan drivers, a driving circuit, and so forth.
2. Description of the Related Art
First, with reference to FIG. 1, the configuration of a plasma display panel (hereinafter referred to as a PDP) will be described. FIG. 1 is an exploded perspective view in schematic form illustrating the configuration of one of pixels in the PDP. On a front substrate 10, two types of electrodes 11 and 12 for display are provided so as to be approximately parallel with one another. The plurality of electrodes 11 and 12 are provided on the entire portion of the front substrate 10 in the order shown in the drawing. These electrodes 11 and 12 are designated as sustaining electrodes. Normally, the sustaining electrodes are formed by transparent electrodes 11i and 12i, and bus electrodes 11b and 12b that are formed thereon. Further, these electrodes 11 and 12 are covered by a dielectric layer 13 having a protection layer 14 (normally MgO) on its surface.
On a back substrate 20, address electrodes 21 are provided along a direction intersecting the sustaining electrodes 11 and 12. These electrodes are covered by a dielectric layer 23. Barriers 25 are provided between the address electrodes 21, and a red fluorescent layer 26R, a green fluorescent layer 26G, and a blue fluorescent layer 26B are provided on the top surface of the dielectric layer 23, the top surface being sandwiched between the barriers 25. The above-described fluorescent layers are also provided on the sides of the barriers 25. FIG. 1 shows only one group of the above-described fluorescent layers 26R, 26G, and 26B. In reality, however, a plurality of fluorescent layers is provided corresponding to the number of pixels of the PDP.
FIG. 2A shows the configuration of a plasma display device (hereinafter referred to a PDP device) having at least one circuit for driving the above-described PDP. The sustaining electrodes 11 and 12 shown in FIG. 1 are designated as X electrodes and Y electrodes. In FIG. 2A, the X electrodes and Y electrodes are indicated by reference characters Xi (i=1, 2, 3, . . . ) and Yj (j=1, 2, 3, . . . ). The X electrodes are simultaneously driven by an X-electrode driver circuit 101, while each of Y electrodes is driven respectively by a Y scan driver 112 connected to a Y-electrode driver circuit 111 that are shown in the drawing. The address electrodes 21 (A electrodes), which are shown in FIG. 1, are indicated by reference characters Ak (k=1, 2, 3, . . . ) in FIG. 2A and are driven by an address driver 121 shown in FIG. 2A.
Next, the connection configuration of a known case is shown in FIG. 3. In this drawing, all of the Y electrodes are sequentially connected to terminals of Y scan drivers 112. Consequently, odd Y electrodes Yo and even Y electrodes Ye are connected to single IC driver, while the X electrodes are connected electrically to the X-electrode driver circuit 101.
Either the lighting (ON) or the non-lighting (OFF) of cells is selected between the address electrodes Ak and the Y electrodes Yj. As a result, some of the cells enter an ON state and emit light by sustaining discharging performed between the X electrodes and the Y electrodes. The sustaining discharging is performed by sustaining pulses applied to the entire surface of the screen. Consequently, a color image is displayed.
FIG. 2B shows an example of the Y scan driver shown in FIG. 2A. Predetermined signals are transmitted to each scan drivers 112-1, . . . , 112-n, which are provided in the Y scan driver 112, via two lines Yp and Yq. In each scan drivers 112-1, . . . , 112-n, switching elements, such as transistors or preferably field effect transistors or so on, are provided. The gates of the switching elements QP11, QN11, . . . , QP1n, QN1n, in this case, are received control signals at predetermined timing from the control circuit unit 131, and then the predetermined voltages as signals are applied to each of Y electrodes Y1, . . . , Yn which are respectively connected to the scan drivers 112-1, . . . , 112n.
Next, the configurations of driving waveforms and a frame will be described with reference to FIGS. 4 and 5. FIG. 4 respectively shows the waveforms applied to X electrode, Y1, . . . , Yn electrodes, and address electrodes.
Basically, the waveforms are divided so as to correspond to three periods including a resetting period, an address period, and sustaining period (a display period), as shown in FIG. 4. In each period, the waveforms shown in the drawing are applied to the X electrodes, Y electrodes, and A electrodes. Initialization is performed in the resetting period, predetermined cells are selected in the address period, and sustaining discharging for display is performed in the sustaining period.
As shown in FIG. 5, each of a plurality of frames for forming an image includes n sub frames corresponding to the weight of display brightness. Each of the sub frames include three periods (a resetting period, an address period, and a sustaining period) shown in FIG. 4. The lengths of the sustaining periods of the sub frames varies as shown in FIG. 5 so that weights are assigned to the lengths for performing a predetermined gradation display.
For performing driving in the address period, each of the scan electrodes (the Y electrodes) is connected to an independent scan driver, as schematically shown in FIG. 6. The plurality of scan drivers forms a group, thereby forming an LSI (the Y scan driver 112). An example of the LSI is shown in FIG. 2B. By using the Y scan driver 112, the scan pulses (voltage value-Vy pulses) in the address period shown in FIG. 4 are output to the Y electrodes.
Switching elements used for the above-described LSI may cause a voltage drop, since the on resistance of the switching elements is high. As a result, an addressing error may occur. Further, since the on resistance is high, much time is required for the rise and fall of the scan pulses. Consequently, the widths of the scan pulses are decreased and the operations become unstable.
The above-described problems are caused when current flowing in the scan electrodes (address current) is large when address discharging is performed in the address period.
Accordingly, an object of the present invention is to provide a method for driving a plasma display panel capable of reducing address current flowing in scan electrodes by spreading the address current, thereby reducing the load on scan drivers, or reducing the number of the scan drivers. Another object of the present invention is to provide a plasma display device.